As is well known, when cell data are accessed in the DRAM, since small charge information stored in the cells must be sensed and further amplified, it takes a long time for accessing the cell data. In this case, the sensing operation must be executed for all the cells belonging to selected word lines, that is, selected rows in a cell array.
By the utilization of the sensing operation, a page mode is well known in which the cells belonging to the same row are accessed at high speed. In this page mode, bit lines and sense amplifiers connected to a number of cells are rewritten compulsorily. Therefore, there inevitably exists a speed limit in the write cycle in this page mode.
To overcome this problem, there has been known a method of executing the page mode without directly transfer data to and from the bit lines (as disclosed in Japanese Published Unexamined (Kokai) Patent Application No. 60-7690, or U.S. Pat. No. 4,608,666). In this method, a row of SRAM cells is arranged along the rows of the DRAM cell array, and data are transferred between the DRAM and an external circuit through the SRAM cells. In this method, since the sense operation and the bit line capacitance of the DRAM cells can be separated from the external data transfer due to the presence of the SRAM cells, it is possible to obtain a high speed access determined by the access cycle to the SRAM.
In the above-mentioned method of accessing the DRAM via the SRAM, however, data transfer is executed between the SRAM and the DRAM in unit of row, some restriction conditions arises in the SRAM cells. In more detail, since the contents of the SRAM cells in which data are not written are undefined, when data are written in a part of the SRAM cells and further the written data are transferred to the DRAM cells, undefined data are written in the DRAM cells corresponding to the SRAM cells to which data are not written, with the result that the data so far stored in the DRAM cells are destroyed. To solve this problem, it is necessary to write data in all the SRAM cells or to transfer the contents of the DRAM cells (to which data are to be transferred) to the SRAM cells previously, before a part of the DRAM cell contents are rewritten.
The problem involved in the prior art memory device will be described in further detail hereinbelow.
In the memory device for accessing a DRAM via a SRAM, to rewrite one row of the DRAM, data of the SRAM are transferred in parallel, and data in one row of the DRAM are rewritten. In this case, where all bit data of the SRAM have been written immediately before data transfer, one row data of the DRAM are replaced with the SRAM data due to parallel transfer. However, in order to rewrite a part of the data in a row of the DRAM, when data are written in a part of bits of the SRAM and data are not written in other remaining bits of the SRAM, the bit data not written in the SRAM are not decided (either of H or L). Under these conditions, when the data are transferred from the SRAM to the DRAM as described above, data of "1" or "0" can be written correctly from the data-written bits to the corresponding bits of the DRAM for data rewrite. However, the undecided data are written from the data-undecided bits to the corresponding bits of the DRAM. Therefore, a part of data not required to be rewritten in the DRAM are written as undecided data, thus data being destroyed.
To prevent the above-mentioned problem, there are two methods as described above. One method is as follows: even when a part of bits in a row of the DRAM are required to be rewritten, all the bits of the SRAM are previously written, and all the bits of the SRAM are transferred to one row of the DRAM. The other method is as follows: as with the case of the ordinary DRAM provided with the SRAM, all the data in a row of the DRAM are transferred to the SRAM, and only a part of the bits already transferred to the SRAM are written, without writing remaining bits (left as they are). In this case, when data are transferred from the SRAM to the row of the DRAM, the rewritten data in the SRAM are transferred to the corresponding bits of the DRAM for data rewrite. The other bits of the DRAM are restored to the original data of their own. In the above-mentioned two prior art methods, however, in spits of the fact that only a part of bits in a row of the DRAM are rewritten, there exists such a problem in that it takes a long time.
As described above, in the conventional memory device, an additional time is required to transfer data from the DRAM cells to the SRAM cells. In addition, since another time required to write data in all the SRAM cells cannot be disregarded and therefore not negligible, some problems arise in that the effect of the high cycle operation is reduced and further a large limitation exists in use of the above-mentioned method.